Design and Implementation of a Fat Tree Network on Chip Master of Science Thesis

System on Chip (SoC) design in the billion transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property blocks. Some of the main problems arise from non-scalable global wires delays, failure to achieve global synchronization and errors due to signal integrity issues. In order to keep a low time-to-market factor new design methodologies must be developed to face this new problems. The desired future SoC methodology must be able to reuse not only the cores but also the interconnection and communication structure. Hence an inevitable decoupling of the communication from the computation resources arises. The Network on Chip (NoC) faces these problems. In a NoC, the different IP blocks communicate by sending packets to one another over a network. The structured network wiring gives well controlled electrical parameters that eliminate timing iterations and enable the use of switches as the basis of the communication system. The Network on Chip concept allows the reusability of the communication infrastructure reducing the time-to-market factor. This master thesis is an attempt of implementing a NoC with a fat tree topology in VHDL. The focus of the work was to build the switch in synthesizable code and to analyze the performance of the network for several configurations. This required the design of a simulation and visualization environment and several test benches. The main objective was to obtain a fairly small switch which made an efficient utilization of the network. Finally a brief comparison between the fat tree and the 2D mesh topology is done.